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ISL88550A
Data Sheet October 12, 2005 FN6168.0
Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator
ISL88550A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two external N-Channel MOSFETs to generate output voltages down to 0.7V from a 2V to 25V input with output currents up to 15A. The LDO can source up to 2.5A and sink up to -2.0A continuously. Both the LDO output and the 10mA reference buffer output can be made to track the REFIN voltage via a built-in resistive divider. These features make the ISL88550A ideally suited for DDR memory applications in desktops, notebooks and graphics cards. The PWM controller in the ISL88550A uses constant-on-time PWM architecture with a programmable switching frequency of up to 600kHz. This control scheme handles wide input/output voltage ratios with ease and provides 100ns "instant-on" response to load transients while maintaining high efficiency and a relatively constant switching frequency. The ISL88550A offers full programmable UVP/OVP and skip mode options ideal in portable applications. Skip mode allows for improved efficiency at lighter loads. The VTT and VTTR outputs track to VREFIN/2. The high bandwidth of this LDO regulator allows excellent transient response without the need for bulk capacitors, thus reducing the cost and size. The buck controller and LDO regulators are provided with independent current limits. Adjustable loss-less fold-back current limit for the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low side synchronous MOSFET. Once over-current is removed, the regulator is allowed to enter soft-start again. This helps minimize power dissipation during short-circuit condition. Additionally, overvoltage and under-voltage protection mechanisms are built in. The ISL88550A allow flexible sequencing and standby power management using SHDNA#, and STBY# inputs.
Features
* Pb-Free Plus Anneal Available (RoHS Compliant)
Buck Controller
* Constant-On PWM with 100ns Load-Step Response * Start-up with Pre-biased Output Voltage * Up to 95% Efficiency * 2V to 25V Input Voltage Range * 1.8V/2.5V Fixed or 0.7V to 3.5V Adjustable Output * 200kHz/300kHz/450kHz/600kHz Switching Frequencies * Programmable Current Limit with Foldback Capability * 1.7ms Digital Soft-Start and Independent Shutdown * Overvoltage/Undervoltage Protection Option * Power-Good Window Comparator
LDO Section
* Fully Integrated VTT and VTTR Capability * VTT has +2.5A/-2.0A Sourcing/Sinking Capability * Start-up with Pre-biased Output Voltage * VTT and VTTR Outputs Track VREFIN/2 * VTT & VTTR 1% of VREFIN/2 * Low All-ceramic Output Capacitor Designs * 1.0V to 2.8V Input REFIN Range * Analog Soft-start Option and Independent Shutdown * Power-Good Window Comparator
Applications
* DDR, DDR II, and DDR III Memory Power Supplies * Desktop Computers * Notebooks and Desknotes * Graphics Cards * Game Consoles * Networking and RAID
Ordering Information
PART NUMBER ISL88550AIRZ (See Note) ISL88550AIRZ-T (See Note) PART MARKING ISL88550AIRZ ISL88550AIRZ TEMP RANGE (C) -40 to +85 -40 to +85 PACKAGE 28 Ld 5x5 Thin QFN (Pb-free) PKG. DWG. # L28.5x5B
28 Ld 5x5 Thin QFN Tape and Reel (Pb-free) L28.5x5B
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL88550A Pinout
ISL88550A (28 LD TQFN) TOP VIEW
SHDNA# PGND1 23 SKIP# AVDD GND
28 TON OVP/UVP REF ILIM POK1 POK2 STBY# 1 2 3 4 5 6 7 8 SS
27
26
25
24
22 21 20 19 18 17 16 15 LGATE BOOT PHASE UGATE VIN OUT FB
9 VTTS
10 VTTR
11 PGND2
12 VTT
13 VTTI
14 REFIN
2
VDD
TPO
FN6168.0 October 12, 2005
ISL88550A
Absolute Maximum Ratings
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +25V VDD, AVDD, VTTI to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V SHDNA#, REFIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V SS, POK1, POK2, SKIP#, ILIM, FB to GND . . . . . . . . . . -0.3V to 6V STBY#, TON, REF, UVP/OVP to GND. . . . . . . .-0.3V to AVDD+0.3V OUT, VTTR to GND . . . . . . . . . . . . . . . . . . . . . .-0.3V to AVDD+0.3V LGATE to PGND1 . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V UGATE to PHASE . . . . . . . . . . . . . . . . . . . . -0.3V to VBOOT +0.3V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V PHASE to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +33V VTT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VTTI+0.3V VTTS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to AVDD+0.3V PGND1, PGND2 to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V REF Short Circuit to GND. . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Thermal Information
Thermal Resistance TQFN Package (Notes 1, 2). . . . . . . . . JA (C/W) 31 JC (C/W) 1.5
Operating Conditions
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -65C + 150C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V, FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, TON = OPEN, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C (Note 3) CONDITIONS MIN TYP MAX UNIT
Note: Following are target specifications. Final limits may change as a result of characterization. PARAMETER MAIN PWM CONTROLLER VIN Input Voltage Range VDD, AVDD Input Voltage Range Output Adjust Range Output Voltage Accuracy (Note 4) FB = OUT FB = GND FB = VDD Soft-Start Ramp Time ON-Time Rising edge of SHDNA# to full current limit VIN = 15V, VOUT = 1.5V (Note 5) TON = GND (600kHz) TON = REF (450kHz) TON = OPEN (300kHz) TON = AVDD (200kHz) Minimum, OFF-Time VIN Quiescent Supply Current VIN Shutdown Supply Current SHDNA# = STBY# = GND (Note 5) 170 213 316 461 200 2 4.5 0.7 0.693 2.470 1.78 0.7 2.5 1.8 1.7 194 243 352 516 300 25 1 2.5 1 2 4.1 4.25 50 219 273 389 571 450 40 5 5 2 10 4.4 25 5.5 3.5 0.707 2.53 1.82 V V V V V V ms ns ns ns ns ns A A mA mA A V mV
Combined AVDD and VDD Quiescent Supply All on (PWM, VTT, & VTTR on), VFB = 0.75V Current STBY# = GND (only VTTR & PWM on), VFB = 0.75V Combined AVDD and VDD Shutdown Supply SHDNA# = STBY# = GND Current AVDD Undervoltage Lockout Threshold Rising edge of AVDD Hysteresis REFERENCE Reference Voltage AVDD = 4.5V to 5.5V; IREF = 0 to 130A 1.98
2
2.02
V
3
FN6168.0 October 12, 2005
ISL88550A
Electrical Specifications
VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V, FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, TON = OPEN, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C (Note 3) (Continued) CONDITIONS IREF = 0 to 50A VREF rising Hysteresis FAULT DETECTION OVP Trip Threshold (Referenced to nominal VOUT) UVP Trip Level Referred to Nominal VOUT POK1 Trip Level Referred to Nominal VOUT Lower level, falling edge, 1% hysteresis Upper level, rising edge, 1% hysteresis POK2 Trip Level Referred to Nominal VTTS and VTTR POK2 Disable Threshold (Measured at REFIN) UVP Blanking Time OVP, UVP, POK_ Propagation Delay POK_ Output Low Voltage POK_ Leakage Current ILIM Adjustment Range ILIM Input Leakage Current Current Limit Threshold (Fixed) PGND1 to PHASE Current Limit Threshold (Adjustable) PGND1 to PHASE Current-Limit Threshold (Negative Direction) PGND1 to PHASE Current-Limit Threshold (Negative Direction) PGND1 to PHASE Current-Limit Threshold (Zero Crossing) PGND1 to PHASE Rising Thermal Shutdown Threshold INTERNAL BOOT DIODE VD Forward Voltage IBOOT_LEAKAGE Leakage Current MOSFET DRIVERS UGATE Gate Driver ON-Resistance LGATE Gate Driver ON-Resistance in High State LGATE Gate Driver ON-Resistance in Low State LGATE rising Dead Time (Additional to Adaptive Delay) UGATE rising VBOOT-VPHASE = 5V 1.5 1.5 0.6 30 30 ns 5 5 3 PVCC-VBOOT, IF = 10mA VBOOT = 25V, PHASE = 20V, PVCC = 5V 0.60 300 0.70 500 V nA Hysteresis ILIM = AVDD VILIM = 2V SKIP# = AVDD SKIP# = AVDD, ILIM = 2V 45 170 -75 50 200 -60 -250 3 150 15 C ISINK = 4mA VPOK_ = 5.5V, VFB = 0.8V, VTTS = 1.3V 0.25 Lower level, falling edge, 1% hysteresis Upper level, rising edge, 1% hysteresis VREFIN rising (Hysteresis = 75mV typical) From rising edge of SHDNA# UVP/OVP = AVDD 110 65 87 107 87.5 107.5 0.7 8 14 10 0.3 1 2.00 0.1 55 235 -45 114 70 90 110 90 110 118 75 93 113 92.5 112.5 0.9 25 % % % % % % V ms s V A V A mV mV mV mV mV 1.93 300 MIN TYP MAX 0.01 UNIT V V mV
Note: Following are target specifications. Final limits may change as a result of characterization. PARAMETER Reference Load Regulation REF Under-voltage Lockout
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FN6168.0 October 12, 2005
ISL88550A
Electrical Specifications
VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V, FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, TON = OPEN, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C (Note 3) (Continued) CONDITIONS MIN TYP MAX UNIT
Note: Following are target specifications. Final limits may change as a result of characterization. PARAMETER INPUTS AND OUTPUTS Logic Input Threshold High (SHDNA#, SKIP#, Rising edge STBY# ) Hysteresis Logic Input Current (SHDNA#, SKIP#, STBY#) FB Input Logic Levels Low (2.5V output) High (1.8V output) Input Bias Current (FB) High Four-Level Input Logic Levels (TON, OVP/UVP) Floating REF Low Logic Input Current (TON, OVP/UVP, Note 4) FB = GND OUT Input Resistance FB = AVDD FB Adjustable Mode OUT Discharge Mode On-Resistance LINEAR REGULATORS (VTTR AND VTT) VTTI Input Voltage Range VTTI Supply Current VTTI Shutdown Current REFIN Input Impedance REFIN range VTT, VTTR UVLO Threshold (Measured at OUT) Soft-Start Charge Current VTT internal MOSFET High-Side OnResistance VTT internal MOSFET Low-Side OnResistance VTT Output Accuracy (Referenced to VTTR) VTT Load Regulation VTT Positive Current Limit VTT Negative Current Limit VTTS Input Current VSS = 0 IVTT = -100mA, VVTTI = 1.5V, AVDD = 4.5V (TJ = 125C) IVTT = 100mA, AVDD = 4.5V (TJ = 125C) VREFIN = 1.8V or 2.5V, IVTT = 5mA VREFIN = 2.5V, IVTT = 0 to 1.5A VREFIN = 1.8V, IVTT = 0 to 1.5A VTT = 0 VTT = VTTI VVTTS = 1.5V, VTT Open -1.25 20 40 2.5 -3.5 -1.5 1 1 3.0 -2.5 0.1 4.0 -2.0 1 1.25 60 IVTT = IVTTR = 0 SHDNA# = STBY# = GND VREFIN = 2.5V 17 1.0 0.01 0.1 4 0.10 0.18 0.28 0.43 1.5 20 1.0 0.1 2.8 1 10 27 2.8 0.2 V mA A k V V A % % % A A A % mA -3 125 90 125 250 180 250 15 2.1 -0.1 AVDD-0.4 3.15 1.65 3.85 2.35 0.5 +3 500 270 500 30 A k k k V 0.1 1.2 1.7 225 -1 1 0.1 2.20 V mV A V V A
VTTR Output Error (Referenced to VREFIN/2) VREFIN = 1.8V, IVTTR = 0mA VTTR Current Limit VTTR = 0 or VTTI
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FN6168.0 October 12, 2005
ISL88550A
Electrical Specifications
VIN = +15V, VDD = AVDD = SHDNA# = STBY# = BOOT = ILIM = 5V, OUT = REFIN = VTTI = 2.5V, FB = SKIP# = OVP/UVP = GND. PGND1 = PGND2 = PHASE = GND, VTTS = VTT, TON = OPEN, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C (Note 3) (Continued) CONDITIONS MIN TYP MAX UNIT
Note: Following are target specifications. Final limits may change as a result of characterization. PARAMETER NOTES: 3. Specifications to -40C are guaranteed by design, not production tested. 4. When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. 5. On-time and off-time specifications are measured from 50% point to 50% point at the UGATE pin with PHASE = GND, VBOOT = 5V, and a 250pF capacitor connected from UGATE to PHASE. Actual in-circuit times may differ due to MOSFET switching speeds.
Pin Descriptions
PIN 1 NAME TON FUNCTION TON On-Time Selection-Control Input. This four-level logic input sets the nominal UGATE on-time. Connect to GND, REF, AVDD, or leave TON unconnected to select the following nominal switching frequencies: TON = AVDD (200kHz) TON =OPEN (300kHz) TON = REF (450kHz) TON = GND (600kHz) Overvoltage/Undervoltage Protection Control Input. This four-level logic input enables or disables the Overvoltage and/or Undervoltage Protection. The overvoltage limit is 116% of the nominal output voltage. The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when OVP is also enabled. Connect the OVP/UVP pin to the following pins for the desired function: OVP/UVP = AVDD (Enable OVP and discharge mode, enable UVP) OVP/UVP = OPEN (Enable OVP and discharge mode, disable UVP) OVP/UVP = REF (Disable OVP and discharge mode, enable UVP) OVP/UVP = GND (Disable OVP and discharge mode, disable UVP) +2.0V Reference Voltage Output. Bypass to GND with a 0.1F (min) bypass capacitor. REF can supply 50A for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDNA#, STBY# are low. Current-Limit Threshold Adjustment for Buck regulator. The current-limit threshold across PGND and PHASE is 0.1 times the voltage at ILIM. Connect ILIM to a resistive-divider (typically from REF) to set the current-limit threshold between 25mV and 200mV (with 0.25V to 2V at ILIM). Connect to AVDD to select the 50mV default current-limit threshold. Buck Power-Good Open-Drain Output. POK1 is low when the Buck output voltage is more than 10% above or below the normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown. LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more than 10% above or below the normal regulation point, which is typically REFIN/2. In standby mode, POK2 responds only to VTTR input. POK2 is low in shutdown, and when VREFIN is less than 0.8V. Stand-by pin. Tie to low for low quiescent mode where the VTT output is disabled with high impedance but the VTTR buffer is kept alive if SHDNA# is high. POK2 takes input from only VTTR in this mode. VTT is discharged to 0V when SHDNA# = GND. PWM output can be on or off depending on the state of SHDNA#. Soft-Start control pin for VTT & VTTR. Connect a capacitor (C9 in Typical Application Circuit) from SS to ground (see Soft-Start capacitor Selection). Leave SS open to disable soft-start. SS discharged to GND when SHDNA# = GND Sensing pin for termination supply output. Normally tied to VTT pin to allow accurate regulation to 1/2 the REFIN voltage. Connected to a resistor divider from VTT to GND to regulate VTT to higher than 1/2 the REFIN voltage. Termination reference voltage. VTTR tracks the value of the VTT output. Power ground for the VTT and VTTR. Termination power supply output. Tie VTT to VTTS to regulate to VREFIN/2. Power supply input voltage for VTT. Normally tied to output of buck regulator for DDR application.
2
OVP/UVP
3
REF
4
ILIM
5
POK1
6
POK2
7
STBY#
8
SS
9
VTTS
10 11 12 13
VTTR PGND2 VTT VTTI
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FN6168.0 October 12, 2005
ISL88550A Pin Descriptions
PIN 14 15 (Continued) FUNCTION External reference input. This is used to regulate the VTT and VTTR outputs to VREFIN/2 Feedback Input for Buck output. Connect to AVDD for a +1.8V fixed output or to GND for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive-divider from the output voltage. FB regulates to +0.7V. Output Voltage Sense Connection. Connect directly to the positive terminal of the buck capacitors. OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the Typical Application Circuit). OUT also serves as the buck output's feedback input in fixed-output modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 20 resistor connected between OUT and ground. Input Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM on-time one-shot timer. This pin can range from 2V to 25V. High-Side Gate-Driver Output. Swings from PHASE to BOOT. UGATE is low when in shutdown or UVLO. External Inductor Connection. Connect PHASE to the input side of the inductor. PHASE is used for both current limit and the return supply of the UGATE driver. Boost Flying-Capacitor Connection. Connect to an external capacitor according to the Typical Application Circuit (Figure 27). See Boost-Supply Diode and Capacitor Selection (BOOT). Synchronous Rectifier Gate-Driver Output. Swings from PGND to VDD. Supply Input for the LGATE Gate Drive. Connect to +4.5V to +5.5V system supply voltage. Bypass to PGND1 with a 4.7F ceramic capacitor. Power Ground for BUCK controller. Connect PGND1 externally to the underside of the exposed pad. Analog Ground for both BUCK and LDO. Connect externally to the underside of the exposed pad. Pulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to enable pulse-skipping operation. Analog Supply for both BUCK and LDO. Bypass to GND with a 1.0F ceramic capacitor. A 10 internal resistor is connected between VDD and AVDD Shutdown Control Input A. Use to control Buck output. A rising edge on SHDNA# clears the overvoltage and undervoltage protection fault latches (See Table 2 and Table 3). Connect AVDD for normal operation. Test Pin. Must be connected to GND externally
NAME REFIN FB
16
OUT
17 18 19 20 21 22 23 24 25 26 27 28
VIN UGATE PHASE BOOT LGATE VDD PGND1 GND SKIP# AVDD SHDNA# TP0
Typical Operating Characteristics
VIN = 12V, VDDQ = 1.8V, TON = GND, SKIP# = AVDD, circuit of Figure 28, TA = 25C, unless otherwise noted.
100 90 80 EFFICIENCY (%) 3VIN-SKIP 12VIN-SKIP FREQUENCY (kHz)
700 3VIN-PWM 600 12VIN-PWM 500 400 300 200 100 0 0.001 3VIN-SKIP 12VIN-SKIP 25VIN-SKIP 25VIN-PWM
70 25VIN-SKIP 60 50 40 30 20 10 0 0.001 0.01 0.1 LOAD (A) 1 10 12VIN-PWM 25VIN-PWM 3VIN-PWM
0.01
0.1 LOAD (A)
1
10
FIGURE 1. EFFICIENCY vs LOAD - 1.8V (TON = GND)
FIGURE 2. SWITCHING FREQUENCY vs LOAD (TON = GND)
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FN6168.0 October 12, 2005
ISL88550A Typical Operating Characteristics
(Continued)
VIN = 12V, VDDQ = 1.8V, TON = GND, SKIP# = AVDD, circuit of Figure 28, TA = 25C, unless otherwise noted.
700 675 650 FREQUENCY (kHz) FREQUENCY (kHz) 625 600 575 550 525 500 475 450 425 400 4 6 8 10 12 14 16 18 20 22 24 26 450 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) IOUT = 0A IOUT = 12A 590 570 550 530 510 490 470 IOUT = 0A IOUT = 12A
VIN (V)
FIGURE 3. SWITCHING FREQUENCY vs INPUT VOLTAGE (TON = GND)
FIGURE 4. SWITCHING FREQUENCY vs TEMPERATURE
(TON = GND)
1.815 1.810 1.805 3VIN-SKIP VDDQ (V) VDDQ (V) 1.800 1.795 1.790 1.785 25VIN-PWM 12VIN-PWM 25VIN-SKIP 12V -SKIP IN
1.800
1.795 IOUT = 0A 1.790 IOUT = 12A 1.785
1.780 1.780 1.775 0.001 3VIN-PWM 1.775 0.01 0.1 LOAD (A) 1 10 4 6 8 10 12 14 16 VIN (V) 18 20 22 24 26
FIGURE 5. VDDQ REGULATION vs LOAD - 1.8V
FIGURE 6. VDDQ OUTPUT vs INPUT VOLTAGE - 1.8V
60 50 OUTPUT RIPPLE (mV) 40 30 20 10 0 0.001 3VIN-SKIP 3VIN-PWM 25VIN-SKIP 25VIN-PWM 12VIN-SKIP 12VIN-PWM VTT (V)
0.950 0.940 0.930 0.920 0.910 0.900 0.890 0.880 0.870 0.860 0.01 0.1 LOAD (A) 1 10 0.850 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5
LOAD (A)
FIGURE 7. OUTPUT RIPPLE vs LOAD - 1.8V (TON = GND)
FIGURE 8. VTT REGULATION vs VTT LOAD
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FN6168.0 October 12, 2005
ISL88550A Typical Operating Characteristics
(Continued)
VIN = 12V, VDDQ = 1.8V, TON = GND, SKIP# = AVDD, circuit of Figure 28, TA = 25C, unless otherwise noted.
IVTT=1.5A, IVTTR=15mA 0.95 0.94 0.93 VTTR (mV) 0.92 0.91 0.90 0.89 0.88 0.87 0.86 0.85 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 20s/DIV 10A 0A IVDDQ 10A/DIV VTTR 100mV/DIV VTT 100mV/DIV VDDQ 100mV/DIV
LOAD (A)
FIGURE 9. VTTR REGULATION vs VTTR LOAD
IVDDQ=12A, IVTTR=15mA
FIGURE 10. LOAD TRANSIENT (VDDQ)
VDD=5V, IVDDQ=12A, IVTT=1.5A, IVTTR=15mA
VDDQ 100mV/DIV VTT 100mV/DIV VTTR 100mV/DIV IVTT 2A/DIV
VDDQ 1V/DIV VTT 1V/DIV VTTR 1V/DIV VIN 10V/DIV
20s/DIV
100s/DIV
FIGURE 11. LOAD TRANSIENT (VTT -1.5A TO 1.5A)
VDD=5V, IVDDQ=12A, IVTT=1.5A, IVTTR=15mA
FIGURE 12. POWER-UP WAVEFORMS
IVDDQ=12A, IVTT=1.5A
VDDQ 1V/DIV VTT 1V/DIV VTTR 1V/DIV VIN 10V/DIV
VDDQ 1V/DIV VTT 500mV/DIV POK1 5V/DIV SHDNA# 5V/DIV
100s/DIV
1ms/DIV
FIGURE 13. POWER-DOWN WAVEFORMS
FIGURE 14. VDDQ STARTUP AND SHUTDOWN INTO HEAVY LOAD, DISCHARGE DISABLED
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FN6168.0 October 12, 2005
ISL88550A Typical Operating Characteristics
(Continued)
VIN = 12V, VDDQ = 1.8V, TON = GND, SKIP# = AVDD, circuit of Figure 28, TA = 25C, unless otherwise noted.
RVDDQ=10, RVTT=20 IVTT=1.5A, IVTTR=15mA
VDDQ 1V/DIV VTT 500mV/DIV POK1 5V/DIV SHDNA# 5V/DIV
VTT 500mV/DIV VTTR 500mV/DIV POK2 1V/DIV
STBY# 5V/DIV
2ms/DIV
200s/DIV
FIGURE 15. VDDQ STARTUP AND SHUTDOWN INTO LIGHT LOAD, DISCHARGE ENABLED
FIGURE 16. VTT, VTTR STARTUP AND SHUTDOWN
UVP DISABLE, FOLDBACK CURRENT LIMIT VDDQ 1V/DIV
UGATE 2V/DIV VDDQ 500mV/DIV LGATE 2V/DIV VTT 500mV/DIV IVDDQ 10A/DIV VIN 10V/DIV
IIN 5A/DIV
50s/DIV
100s/DIV
FIGURE 17. OVERVOLTAGE AND TURN-OFF OF BUCK OUTPUT
UVP ENABLE
FIGURE 18. SHORT CIRCUIT AND RECOVERY OF VDDQ
VDDQ 1V/DIV IVDDQ 10A/DIV VIN 10V/DIV
VTT 500mV/DIV
IIN 5A/DIV
IVTT 2A/DIV
50s/DIV
100s/DIV
FIGURE 19. SHORT CIRCUIT AND RECOVERY OF VDDQ
FIGURE 20. SHORT CIRCUIT AND RECOVERY OF VTT
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FN6168.0 October 12, 2005
ISL88550A
VIN
tOFF
TON
ON TIME COMPUTE tON TRIG 1-SHOT Q
TRIG Q 1-SHOT
BOOT
UGATE
S Q R
PHASE
INTREF + + -
VDD
S 1.16 X INTREF + Q R
LGATE
+
PGND1
OVP/UVP
BUCK ON/OFF
SHDNA#
SHUTDOWN Bias ON/OFF DECODER
1.0V 20mSec Timer POR VOUT=1.8V VOUT=2.5V VDD DISCHARGE LOGIC N 10 PHASE ZERO CROSSING PHASE
STBY#
+ 0.7 x INTREF VTT ON/OFF VTTR ON/OFF
POK1
-
INTREF+10% INTEREF-10% + + -
N
FB DECODER
INTREF
2V REFERENCE
FB
INTREF/2+10%
REFIN/2 OUT 0.1V + VDD N 10k
POK2
INTEREF/2-10% + -
10k
N
+ POWER DOWN VDD N + + CURRENT VTT ILIM LIMIT OUT INTREF/2+10% INTEREF/2-10% + PGND2
-
SS
FIGURE 21. FUNCTIONAL BLOCK DIAGRAM
11
+
-
OVP/UVP LATCH Blank
+ VDD-1V
-
QUAD Level Decoder
ILIM
SKIP#
OUT
AVDD GND
REF VTTS REFIN VTTI
+
-
VTT
PGND2
VTTR
FN6168.0 October 12, 2005
ISL88550A Detailed Description
The ISL88550A combines a synchronous buck PWM controller, an LDO linear regulator, and a 10mA reference output. The buck controller drives two external N-Channel MOSFETs to deliver load currents up to 15A and generates voltages down to 0.7V from a +2V to +25V input. The LDO Linear Regulator can source up to 2.5A and sink up to -2.0A continuously. These features make the ISL88550A ideally suited for DDR memory application. The ISL88550A buck regulator is equipped with a fixed switching frequency up to 600kHz constant on-time PWM architecture. This control scheme handles wide input/output voltage ratios with ease, and provides 100ns "instant-on" response to load transients while maintaining high efficiency with relatively constant switching frequency. The buck controller, LDO, and buffered reference output are provided with independent current limits. Lossless fold-back current limit in the buck regulator is achieved by monitoring the drain to source voltage drop of the low side FET. The ILIM input is used to adjust this current limit. Over-voltage protection is achieved by latching the low side synchronous FET on and the high side FET off when the output voltage is over 116% of its set output. It also features an optional under voltage protection by latching the MOSFET drivers to the OFF state during an over current condition when the output voltage is lower than 70% of the regulated output. Once the over current condition is removed, the regulator is allowed to soft-start again. This helps minimize power dissipation during a short circuit condition. The current limit in the LDO and buffered reference output is +3.0A/-2.5A and 40mA respectively and neither have the over or under voltage protection. When the current limit in either output is reached, the output no longer regulates the voltage, but will regulate the current to the value of the current limit. of MOSFETs Q1 and Q2, (at VGS = 5V), in the Typical Application Circuit and SW is the switching frequency.
Free-Running Constant-On-Time PWM
The constant on-time PWM control architecture is a pseudo fixed frequency, constant on-time, current-mode regulator with voltage feed forward (Figure 21). This architecture relies on the output filter capacitor's ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to the output voltage. Another one-shot sets a minimum off time of 300ns typically. The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out.
ON-Time One Shot (TON)
The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable oneshot includes circuitry that varies the on-time in response to input and output voltages. The high-side switch on-time is inversely proportional to the input voltage (VIN) and is proportional to the output voltage:
t on = K x
(VOUT + ILOAD x RDS(ON)Q2 )
VIN
where K (the on time scale factor) is set by the TON input connection (Table 1) and RDS(ON)Q2 is the on-resistance of the synchronous rectifier (Q2) in the Typical Application Circuit. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: 1. The frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band. 2. The inductor ripple-current operating point remains relatively constant, resulting in an easy design methodology and predictable output voltage ripple. The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics Table (approximately 12.5% at 600kHz and 450kHz and 10% at 200kHz and 300kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics Table can vary over a wider range. For example, the 600kHz setting typically runs approximately 10% slower with inputs much greater than 5V due to the very short on-times required. The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics Table are influenced by resistive losses and by switching delays in the high-side MOSFET. Resistive losses, which include the inductor, both MOSFETs, the output capacitors ESR, and any PC board copper losses
+5V Bias Supply (VDD and AVDD)
The ISL88550A requires an external +5V bias supply in addition to the input voltage (VIN). Keeping the bias supply external to the IC improves the efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and the gate drivers. VDD, AVDD and VIN can be connected together if the input source is a fixed +4.5V to +5.5V supply. VDD is the supply input for the Buck regulator's MOSFET drivers, and AVDD supplies the power for the rest of the IC. The current from the AVDD and VDD power supply must supply the current for the IC and the gate drive for the MOSFET's. This maximim current can be estimated as:
IBIAS = IVDD + IAVDD + fSW x(Q G1 + QG2 )
Where IVDD, + IAVDD are the quiescent supply currents into VDD and AVDD and QG1 and QG2 are the total gate charges
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in the output and ground, tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective on-time. The dead time occurs only in PWM mode, (SKIP# = VDD), and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes PHASE to go high earlier than normal, extending the on-time by a period equal to the UGATE-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is:
fSW = VOUT + VDROP1 t ON (VIN + VDROP2 )
The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by selection of inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed), and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the ISL88550A regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP# = GND and ILOAD < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error comparator threshold by approximately 1.5% due to slope compensation.
I = t VIN- V OUT L
where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchronous rectifier, the inductor, and any PC board resistances; VDROP2 is the sum of the resistances in the charging path, including the high-side switch (Q1 in Typical Application Circuit), the inductor, and any PC board resistances, and tON is the one-shot on-time (see section on On-time Oneshot (TON).
In skip mode, (SKIP# = GND), an inherent automatic switchover to PFM takes place at light loads (Figure 22). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator differentially senses the inductor current across the synchronous rectifier MOSFET (Q2 in Typical Application Circuit). Once VPGND PHASE drops below 5% of the current-limit threshold, (3mV for the default 50mV current-limit threshold), the comparator forces LGATE low (see Block Diagram Figure 21). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductorcurrent operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to one-half the peak-to-peak ripple current, which is a function of the inductor value (see Figure 22). This threshold is relatively constant, with only a minor dependence on the input voltage (VIN).
V x K VIN - VOUT ILOAD(SKIP ) = OUT 2L VIN
Inductor Current
Automatic Pulse-Skipping Mode (SKIP# = GND)
IPEAK
ILOAD=IPEAK/2
0
ON-TIME
TI M E
FIGURE 22. PULSE SKIPPING/DISCONTINUOUS CROSSOVER POINT
where K is the on-time scale factor (see Table 1). For example, in the Typical Applications Circuit (K = 1.7s, VOUT = 2.5V, VIN = 12V, and L = 1H), the pulse-skipping switchover occurs at:
2.5 V x 1.7s 12V - 2.5 V = 1.68 A 2 x 1H 12V
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TABLE 1. APPROXIMATE K-FACTOR ERRORS TYPICAL K TON SETTING FACTOR (s) 200kHz (TON = AVDD) 300kHz (TON = OPEN) 450kHz (TON = REF) 600kHz (TON = GND) 5.0 3.3 2.2 1.7 K-FACTOR ERROR (10%) 10 10 12.5 12.5 MINIMUM VIN AT VOUT = 2.5V (h = 1.5, SEE DROPOUT PERFORMANCE SECTION) 3.15 3.47 4.13 5.61 TYPICAL APPLICATION 4-Cell Li+ Notebook 4-Cell Li+ Notebook 3-Cell Li+ Notebook +5V input
COMMENTS Use for absolute best efficiency Considered mainstream by current standards Useful in 3 cell systems for lighter loads Good operating point for compound buck designs or desktop circuts.
Force PWM Mode (SKIP# = AVDD)
The low-noise forced-PWM mode, (SKIP# = AVDD), disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gate drive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while UGATE maintains a duty factor of VOUT/VIN. ForcedPWM mode keeps the switching frequency fairly constant. However, forced-PWM operation comes at a cost where the no-load VDD bias current remains between 2mA and 20mA due to the external MOSFETs gate charge and switching frequency. Forced-PWM mode is most useful for reducing audio frequency noise, improving load-transient response, and providing sink current capability for dynamic output voltage adjustment.
A 2A to 20A divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the current limit threshold voltage (from PHASE to PGND1) is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 50mV when ILIM is connected to AVDD. The logic threshold for switchover to the 50mV default value is approximately AVDD - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen between PHASE and PGND1.
Current Limit Buck Regulator (ILIM)
VALLEY CURRENT LIMIT The current-limit circuit for the Buck Regulator portion of the ISL88550A employs a unique "valley" current sensing algorithm that senses the voltage drop across PHASE and PGND1 and uses the on-resistance of the rectifying MOSFET (Q2 in the Typical Application Circuit) as the current sensing element. If the magnitude of the current sense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figure 24). With Valley Current Limit sensing, the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor current ripple. Therefore, the exact current limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and input voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. In forced-PWM mode, the ISL88550A also implements a negative current limit to prevent excessive reverse inductor currents when the Buck Regulator output is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when VILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. 14
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ISL88550A
REF
C REF
LX
1.0V
FIGURE 23. ADJUSTABLE CURRENT LIMIT THRESHOLD
I PEAK
I LOAD INDUCTOR CURRENT
I
I LIMIT I LOAD(MAX)
I I LIM ( VAL ) = I LOAD - ----2
FIGURE 24. VALLEY CURRENT-LIMIT THRESHOLD
POR, UVLO, and Soft-Start
Internal Power-on reset (POR) occurs when AVDD rises above approximately 2V, resetting the fault latch and the soft-start counter, powering up the reference, and preparing the Buck Regulator for operation. Until AVDD reaches 4.25V (typical), AVDD undervoltage lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling UGATE low and holding LGATE low when OVP and shutdown discharge are disabled (OVP/UVP = REF or GND) or forcing LGATE high when OVP and shutdown discharge are enabled (OVP/UVP = AVDD or OPEN). See Table 3 for detailed truth table for OVP/UVP and Shutdown settings. When AVDD rises above 4.25V, the controller activates the Buck Regulator and initializes the internal soft start. The Buck Regulator's internal soft-start allows a gradual increase of the current limit level during startup to reduce the input surge currents. The ISL88550A divides the soft-start period into five phases. During the first phase, the controller limits
15
+
-
+ VDD-1V
ILIM
R
9R
R A
RB
C ILIM
the current limit to only 20% of the full current limit. If the output does not reach regulation within 425s, soft start enters the second phase, and the current limit is increased by another 20%. This process repeats until the maximum current limit is reached, after 1.7ms, or when the output reaches the nominal regulation voltage, whichever occurs first. Adding a capacitor in parallel with the external ILIM resistors creates a continuously adjustable analog soft-start function for the Buck Regulator's output. For most applications, LDO soft start is not necessary because of output charging current is limited to approximately 3.0A. For 20F LDO output capacitors, the minimum rise time is about 30s. However, soft start in the LDO section can be realized by tying a capacitor between the SS pin and ground. When STBY# is driven low, or during thermal shutdown of the LDO's, the SS capacitor is discharged. When STBY# is driven high or when the thermal limit is removed, an internal 4A (typ) current charges the SS capacitor. The resulting linear ramp voltage on SS linearly increases the current-limit comparator thresholds to both the VTT and VTTR outputs, until full current limit is attained when SS reaches approximately 1.6V. This lowering of the current limit during start-up limits the initial in-rush current peaks, particularly when driving higher output capacitances. For good tracking, choose the value of the SS cap less than 390pF. Leave SS floating to disable the softstart feature.
Power OK (POK1)
POK1 is an open-drain output for a window comparator that continuously monitors VOUT. POK1 is actively held low when SHDNA# is low and during the Buck Regulator outputs softstart. After the digital soft-start terminates, POK1 becomes high impedance as long as the output voltage is within 10% of the nominal regulation voltage set by FB. When VOUT
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drops 10% below or rises 10% above the nominal regulation voltage, the ISL88550A pulls POK1 low. Any fault condition forces POK1 low until the fault latch is cleared by toggling SHDNA# or cycling AVDD power below 1V. For logic level output voltages, connect an external pull up resistor between POK1 and AVDD. A 100K resistor works well in most applications. Note that the POK1 window detector is completely independent of the overvoltage and undervoltage protection fault detectors and the state of VTTS and VTTR. below their nominal regulation voltage, the ISL88550A pulls POK2 low. For logic level output voltages, connect an external pull up resistor between POK2 and AVDD. A 100K resistor works well in most applications. Note that the POK2 window detector is completely independent of the overvoltage and undervoltage protection fault detectors and the state of VDDQ.
Current Limit (LDO for VTT and VTTR buffer)
The VTT output is a linear regulator that regulates the input (VTTI) to 1/2 the VREFIN voltage. The feedback point for VTT is at the VTTS input (see Figure 21 Block Diagram). VTT is capable of sourcing up to 2.5A and sinking up to -2.0A continuously. The current limit for VTT and VTTR is typically +3.0A/-2.5A and 40mA respectively. When the current limit for either output is reached, the outputs regulate the current not the voltage. The current limits for both VTT and VTTR can be reduced from their full values by forcing the voltage at the SS pin below 1.6V (typ), or by tying a resistor Rss between the SS pin and ground such that 4A*Rss is less than 1.6V. POK2 is pulled low when REFIN is < 0.8V.
SHDNA# and Output Discharge
The SHDNA# input corresponds to the Buck Regulator and places the Buck Regulator's portion of the IC in a low power mode (see Electrical Characteristics Table). SHDNA# is also used to reset a fault signal such as an overvoltage or undervoltage fault. When output discharge is enabled (OVP/UVP = AVDD or open) and SHDNA# is pulled low, or if UVP is enabled (OVP/UVP = AVDD) and VOUT falls to 70% of its regulation set point, the ISL88550A discharges the Buck Regulator output (via the OUT input) through an internal 15 switch to ground. While the output is discharging, the PWM controller is disabled, but the reference remains active to provide an accurate threshold. When output discharge is disabled (OVP/UVP = REF or GND), the controller does not actively discharge the Buck Output. Under these conditions, the Buck Output discharge rate is determined by the load current and its output capacitance. The Buck Regulator detects and latches the discharge mode state set by OVP/UVP setting on startup.
Fault Protection
The ISL88550A provides overvoltage/undervoltage fault protection in the buck controller. Select OVP/UVP to enable and disable fault protection as shown in Table 3. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. Any VDDQ shutdown due to OVP, UVP, OTP or SHDNA# = 0 should also discharge VTT to 0V. * Overvoltage Protection (OVP) When the output voltage rises above 114% of the nominal regulation voltage and OVP is enabled (OVP/UVP = AVDD or open), the OVP circuit sets the fault latch, shuts down the PWM controller, and immediately pulls UGATE low and forces LGATE high. This turns on the synchronous rectifier MOSFET with 100% duty cycle, rapidly discharging the output capacitor and clamping the output to ground. Note that immediately latching LGATE high can cause the output voltage to go slightly negative due to energy stored in the output LC circuit at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. Toggle SHDNA# or cycle AVDD power below 1V to clear the fault latch and restart the controller. OVP is disabled when OVP/UVP is connected to REF or GND (see Table 3). OVP only applies to the Buck Output. The VTT and VTTR Outputs do not have overvoltage protection. When VDDQ is discharged to 0V due to OVP, VTT is also discharged to 0V.
STBY#
The STBY# input is an active low input that is used to shutdown only the VTT output. When STBY# is low, VTT is high impedance, but the VTTR output is still active if SHDNA# is high. VTT and VTTR are pulled to 0V when SHDNA is low.
TABLE 2. SHUTDOWN AND STANDBY CONTROL LOGIC SHDNA# GND STBY# X BUCK OUTPUT OFF VTT OFF (Discharge to 0V) OFF (High Impedance) ON VTTR OFF (Tracking 1/2 REFIN) ON
AVDD
GND
ON
AVDD
AVDD
ON
ON
Power OK (POK2)
POK2 is the open-drain output for a window comparator that continuously monitors the VTTS input and VTTR output. POK2 is high impedance as long as the output voltage is within 10% of the nominal regulation voltage as set by REFIN. When VVTTS or VVTTR rise 10% above or 10% 16
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TABLE 3. OVP/UVP FAULT PROTECTION OVP/UVP AVDD DISCHARGE 15 internal switch ON UGATE/LGATE is low when SHDNA# = low for normal shutdown 15 internal switch ON UGATE/LGATE is low when SHDNA# = low for normal shutdown 15 internal switch OFF UGATE/LGATE is low when SHDNA# = low 15 internal switch OFF UGATE/LGATE is low when SHDNA# = low UVP PROTECTION Enabled. OVP PROTECTION Enabled. UGATE pulled low and LGATE forced high if OVP detected Enabled. UGATE pulled low and LGATE forced high if OVP detected Disabled Disabled
OPEN
Disabled
REF GND
Enabled. Disabled
* Undervoltage Protection (UVP) When the output voltage drops below 70% of its regulation voltage, and UVP is enabled (OVP/UVP = AVDD or REF), the controller sets the fault latch and begins the discharge mode (see the Shutdown and Output Discharge section). UVP is ignored for 14ms (minimum), after startup or after a rising edge on SHDNA#. Toggle SHDNA# or cycle AVDD power below 1V to clear the fault latch and restart the controller. UVP is disabled when OVP/UVP is left open or connected to GND (see Table 3). UVP only applies to the Buck Output. The VTT and VTTR Outputs do not have under voltage protection. When VDDQ is discharged to 0V due to UVP, VTT is also discharged to 0V. * Thermal Fault Protection The ISL88550A features a thermal fault protection circuit, which monitors the Buck Regulator of the IC, the Linear Regulator (VTT) and the buffered output (VTTR). When the junction temperature of the ISL88550A rises above +150C, a thermal sensor activates the fault latch, pulls POK1 low, and shuts down the buck converter using discharge mode regardless of the OVP/UVP setting, and VTT is also discharged to 0V. Toggle SHDNA# or cycle AVDD power below 1V to reactivate the controller after the junction temperature cools by 15C.
inductor saturation rating, and the design of the currentlimit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. * Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. * Inductor Operating Point. This choice provides tradeoffs: size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP# = low at light loads), the inductor value also determines the load current value at which PFM/PWM switch over occurs.
Design Procedure
Firmly establish the input voltage range (VIN) and maximum load current in the buck regulator before choosing a switching frequency and inductor operating point (ripplecurrent ratio or LIR). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range. The maximum value (VIN (MAX)) must accommodate the worst-case, high AC adapter voltage. The minimum value (VIN (MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice, lower input voltages result in better efficiency. * Maximum Load Current. There are two values to consider. The peak load current (IPEAK) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection,
Setting the Output Voltage (Buck)
Preset Output Voltages
The ISL88550A allows the selection of common voltages without requiring external components (Figure 25). Connect FB to GND for a fixed 2.5V output, to AVDD for a fixed 1.8V output, or connect FB directly to OUT for a fixed 0.7V output.
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Setting the VTT and VTTR Voltages (LDO)
ISL88550A TO ERROR AMPLIFIER FB 1.8V(FIXED) OUT
2.5V (FIXED)
The Termination Power Supply Output (VTT) can be set by two different methods. First, the VTT output can be connected directly to the VTTS input to force VTT to regulate to VREFIN/2. Secondly, VTT can be forced to regulate higher than VREFIN/2 by connecting a resistive divider from VTT to VTTS. The maximum value for VTT will be the VVTTI VDROPOUT where VDROPOUT = IVTT x 0.3 typically. The Termination Reference Voltage (VTTR) will follow 1/2 VREFIN.
REF (2.0V)
Inductor Selection (Buck)
0.1 x REF (0.2V)
The switching frequency and inductor operating point determine the inductor value as follows:
L= VOUT (VIN - VOUT ) VIN x fSW x ILOAD(MAX ) x LIR
FIGURE 25. DUAL-MODE FEEDBACK DECODER
Setting the Buck Regulator Output (VOUT) with a Resistive Voltage-Divider at FB
The Buck Regulator output voltage can be adjusted from 0.7V to 3.5V using a resistive voltage-divider (Figure 26). The ISL88550A regulates FB to a fixed reference voltage (0.7V). The adjusted output voltage is:
R V VOUT = VFB 1 + C + RIPPLE RD 2
For example: ILOAD(MAX) = 12A, VIN = 12V, VOUT = 2.5V, SW = 300kHz, 30% ripple current or LIR = 0.3
L= 2.5V (12 V - 2.5 V ) = 1.8H 12 V x 300kHz x 12 A x 0.3
Where VFB is 0.7V and
VRIPPLE = LIR x ILOAD x RESR
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK):
LIR IPEAK = ILOAD(MAX ) 1 + 2
PHASE LGATE PGND1 ISL88550A GND Q2
L COUT
Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values.
Input Capacitor Selection (Buck)
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents:
RC
OUT
IRMS = ILOAD
VOUT VIN
V 1 - OUT VIN

FB RD
FIGURE 26. SETTING VOUT WTH A RESISTIVE VOLTAGE DIVIDER
For most applications, non-tantalum chemistry capacitors (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the ISL88550A are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime.
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Output Capacitor Selection (Buck)
The output filter capacitor must have low enough equivalent series resistance (RESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to satisfy stability requirements. For processor core voltage converters and other applications in which the output is subject to violent load transients, the output capacitor's size depends on how much RESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
RESR VSTEP ILOAD(MAX )
VTTI Input Cap Selection (LDO)
Both the VTT and VTTR output stages are powered from the same VTTI input. Their output voltages are referenced to the same REFIN input. The value of the VTTI bypass cap is chosen to limit the amount of ripple/noise at VTTI, or the amount of voltage dip during a load transient. Typically, a ceramic cap of at least 10F should be used. This value is to be increased with larger load current, or if the trace from the VTTI pin to the power source is long and has significant impedance. Furthermore, to prevent undesirable VTTI bounce from coupling back to the REFIN input and possibly causing instability in the loop, the REFIN pin should ideally tap its signal from a separate low impedance DC source rather than directly to the VTTI input. If the latter is unavoidable, increase the amount of bypass at the VTTI input and add additional bypass at the REFIN pin.
In applications without large and fast load transients, the output capacitor's size often depends on how much RESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a step down controller is approximately equal to the total inductor ripple current multiplied by the output capacitor's RESR. Therefore, the maximum RESR required to meet ripple specifications is:
RESR VRIPPLE ILOAD(MAX ) x LIR
MOSFET Selection (Buck)
The ISL88550A drive external, logic-level, N-Channel MOSFETs as the circuit-switch elements. The key selection parameters: Maximum Drain-To-Source Voltage (VDSS): should be at least 20% higher than input supply rail at the high side MOSFET's drain. Choose the MOSFETs with rated RDS(ON) at VGS = 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET that has a conduction loss equal to switching loss at nominal input voltage and maximum output current (see below). For low-side MOSFET, make sure that it does not spuriously turn on because of dV/dt caused by high-side MOSFET turning on, as this would result in shoot through current degrading the efficiency. MOSFETs with a lower QGD to QGS ratio have higher immunity to dV/dt. For proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side MOSFET, worst case is at VIN(MAX); for high-side MOSFET, it could be either at VIN(MIN) or VIN(MAX)). The high-side MOSFET and low-side MOSFET have different loss components due to the circuit operation. The low-side MOSFET operates as a zero voltage switch; therefore, major losses are 1. The channel conduction loss (PLSCC) 2. The body diode conduction loss (PLSDC) 3. The gate-drive loss (PLSDR)
V PLSCC = 1 - OUT VIN x ILOAD 2 xRDS(ON)
The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OSCONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
VTT Output Cap Selection (LDO)
Place 2 x 10F 0805 ceramic capacitor as close to VTT output as possible for optimum performance of output loading up to +2.5A/-2.0A. In most applications, it is not necessary to add more capacitance. However, optional additional capacitances can be added further away (>1.5in) from VTT output.
VTTR Output Cap Selection (LDO)
The VTTR buffer is a scaled down version of the VTT regulator, with much smaller output transconductance. Its compensation cap can therefore be smaller, and its ESR larger, than what is required for its larger counterpart. For typical applications requiring load current up to 20mA, a ceramic cap with a minimum value of 1F is recommended (ESR<0.3). Tie this cap between VTTR and analog ground plane.
PLSDC = 2ILOAD x VF x t DT x fSW
where VF is the body-diode forward-voltage drop, tDT is the dead time (30ns), and fSW is the switching frequency.
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ISL88550A
Because of the zero-voltage switch operation, the low-side MOSFET gate-drive loss occurs as a result of charging and discharging the input capacitance, (CISS). This loss is distributed among the average LGATE driver's pull-up and pull-down resistance, RLGATE (1), and the internal gate resistance (RGATE) of the MOSFET (~2). The driver power dissipated is given by:
PLSDR = CISS x VGS 2 x fSW x R GATE R GATE + RLGATE
PHASE's rising and falling transitions and can interfere with circuit performance and generate EMI. A series R-C snubber may be added across the lower MOSFET to dampen this ringing. Below is the procedure for selecting the value of the series R-C circuit: 1. Connect a scope probe to measure PHASE to GND, and observe the ringing frequency, R. 2. Find the capacitor value (connected from PHASE to GND) that reduces the ringing frequency by half. The circuit parasitic capacitance (CPAR) at PHASE is then equal to 1/3 the value of the added capacitance above. The circuit parasitic inductance (LPAR) is calculated by:
L PAR =
The high-side MOSFET operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (PHSCC), the VI overlapping switching loss (PHSSW), and the drive loss (PHSDR). The high-side MOSFET does not have body-diode conduction loss because the diode never conducts current:
PHSCC = VOUT x ILOAD 2 xRDS(ON) VIN
(2 x fR ) 2x CPAR
1
Use RDS(ON) at TJ(MAX).
PHSSW = VIN x ILOAD x fSW x Q GS + QGD IGATE
The resistor for critical dampening (RSNUB) is equal to 2 x R x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least 2 to 4 times the value of the CPAR in order to be effective. The power loss of the snubber circuit (PRSNUB) is dissipated in the resistor and can be calculated as:
PRSNUB = CSNUB x VIN 2 xfSW
where IGATE is the average UGATE driver output-current determined by:
IGATE (ON) = 2 .5 V RUGATE + R GATE
where RUGATE is the high-side MOSFET driver's onresistance (1.5 typical) and RGATE is the internal gate resistance of the MOSFET (~2):
PHSDR = Q G x VGS x fSW R GATE x R GATE + RUGATE
where VIN is the input voltage and SW is the switching frequency. Choose an RSNUB power rating that meets the specific application's derating rule for the power dissipation calculated.
Setting the Current Limit (Buck)
The current-sense method used in the ISL88550A makes use of the on resistance (RDS(ON)) of the low side MOSFET (Q2 in Typical Application Circuit). When calculating the current limit, use the worst-case maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each 1C of temperature rise. The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore:
ILOAD(MAX ) x LIR ILIM(VAL ) > ILOAD(MAX ) - 2
where VGS = VDD = 5V. In addition to the losses above, allow about 20% more for additional losses because of MOSFET output capacitances and low-side MOSFET bodydiode reverse recovery charge dissipated in the high-side MOSFET that is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal-resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above-calculated power dissipations. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the lowside switch source, or add resistors in series with UGATE and LGATE to slow down the switching transitions. Adding series resistors increases the power dissipation of the MOSFET, so ensure that this does not overheat the MOSFET.
MOSFET Snubber Circuit (Buck)
Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at
where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the on resistance of Q2 (RDS(ON)Q2). For the 50mV default setting, the minimum valley current-limit threshold is 40mV. Connect ILIM to AVDD for a default 50mV valley current limit threshold. In adjustable mode, the valley current limit threshold is precisely 1/10th the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with
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ISL88550A
ILIM connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10A to prevent significant inaccuracy in the valley currentlimit tolerance. 6. Then R5 can be calculated as:
R5 =
[(VDDQ - (V
ILIM
VDDQ x R 4 x RR1 // R5 - VILIM(0 V ) x R4 - VILIM - VILIM(0 V ) x RR1 // R5
))
(
)
]
7. Then R1 is calculated as:
R1 =
Setting the Foldback Current Limit (Buck)
Alternately, foldback current limit can be implemented if UVP is disabled. Foldback current limit reduces the power dissipation of external components so they can withstand indefinite output overload or short circuit. With automatic recovery after the fault condition is removed. To implement foldback current limit, connect a resistor from VOUT to ILIM (R1 in the typical application circuit), in addition to the resistor-divider network (R4 and R5) used for setting the adjustable current limit. The following is a procedure for calculating the values of R1, R4, and R5: 1. Calculate the voltage, VILIM:
LIR VILIM = 10 x ILOAD(MAX ) x 1 - x RDSON(Q2 ) 2
[R5 - RR1// R5 ]
R5 x RR1 // R5
Boost-Supply Capacitor Selection (Buck)
The boost capacitor should be 0.1F to 4.7F, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum lowside MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-to-source voltage required to keep the high-side MOSFET fully enhanced for lowest on-resistance. This minimum gate to source voltage (VGS(MIN)) is determined by:
VGS(MIN) = VDD x QG CBOOST
2. Pick a percentage of foldback, PFB, from 15% to 40%. 3. Calculate the voltage,VVILIM(0V), when the output is shorted (0V).
where VDD is 5V, QG is the total gate charge of the high-side MOSFET, and CBOOST is the boost capacitor value where CBOOST is C7 in the typical application circuit.
Transient Response (Buck)
REF
ISL88550A ISL88550A/ ISL88551A
VDDQ CREF R4 R1
ILIM R5 GND
The inductor ripple current also affects transient response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
xK 2V + t OFF(MIN) L x ILOAD(MAX ) OUT VIN = (V - VOUT ) x K + t OFF(MIN) 2COUT x VOUT IN VIN
VSAG
FIGURE 27. FOLDBACK CURRENT LIMIT
VILIM(0 V ) = PFB x VILIM
where tOFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 1. The overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as:
VSOAR = ILOAD(MAX ) x L 2 x COUT x VOUT
2
4. The value of R4 can be calculated as:
R4 = 2V - VILIM(0 V ) 10A
5. The parallel combination of R1 and R5 is calculated as:
RR1 // R5 = 2V - R4 10A
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ISL88550A
C3 1F AVDD C9: OPEN SS
ISL88550A
OVP/UVP OVP/UVP 5V BIAS SUPPLY VDD VDD ISL88550A TON VIN VIN SKIP# BOOT BOOT GND UGATE UGATE STBY# C7 PHASE PHASE SHDNA# LGATE LGATE Q2 0.22F C11 220F 220 150 12m 12m PGND1 PGND1 POK2 OUT OUT POK1 R1: 182k ILIM ILIM VTTI R4 200k REF REF C10 0.22F R5 56.2k Q2: IRF7832/30V/5m Q1: IRF7821/30V/9m Q1 L1: FALCO ER1309 1.0H, 35A, 2m 1.0uH, 2m C8: 2x10F C14 470F (OPTIONAL) C5: 4.7F VIN: 4.5V to 25V
VDDQ 1.8V/12A
AVDD
C12 220F 220yF 150yF 12m 12m
C13 1F
R3 100k
R2 100k
1.5V C2 10F VTT: 0.9V1.5A VTT C4 2x10F PGND2
FB FB
AVDD
VTTS
REFIN REFIN 0.9V/10mA VTTR VTTR C6 1F C1 OPEN
FIGURE 28. TYPICAL DDR II APPLICATIONS CIRCUIT
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ISL88550A
C3 1F C9: OPEN SS TON
ISL88550A
AVDD OVP/UVP 5V BIAS SUPPLY VDD C5: 4.7F VIN: 4.5V to 25V VIN SKIP# BOOT GND UGATE STBY# PHASE SHDNA# LGATE Q2 C7 0.22F Q1 L1: FALCO ER1309 1.0H, 35A, 2m C8: 2x10F C14 470F (OPTIONAL) GFXCORE 0.95V/12A C11 330F 9m C12 330F 9m C13 1F
AVDD
R3 100k
R2 100k POK2
PGND1 OUT POK1 R1: 182k ILIM VTTI R4 200k REF VTT FB REFIN 1V/10mA PGND2 VTTR C6 1F C10 0.22F R5 56.2k R6 24.9k GPIO OPEN : GFXCORE = 0.95V GPIO LOW : GFXCORE = 1.20V GPIO Q1: IRF7821/30V/9m Q2: IRF7832/30V/5m
1.8V C2 10F
PCI-e 1.2V/2A
C4 2x10F
R9 1.21k R10 4.99k
VTTS
R7 69.8k
R8 69.8k
FIGURE 29. TYPICAL GFX APPLICATION CIRCUIT
Applications Information
Dropout Performance (Buck)
The output voltage adjustable range for continuous conduction operation is restricted by the non-adjustable minimum off time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using the worse case values for on and off times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (see Table 1). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio 23
h = IUP/IDOWN indicates the controller's ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and VSAG greatly increases, unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:
VOUT + VDROP1 VIN(MIN) = + VDROP2 - VDROP1 1 - h x t OFF(MIN) K
FN6168.0 October 12, 2005
ISL88550A
where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the On- Time OneShot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 1. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. A dropout design example follows: * VOUT = 2.5V * fSW = 600kHz * K = 1.7s * tOFF(MIN) = 450ns * VDROP1 = VDROP2 = 100mV * h = 1.5
2.5 V + 0.1V VIN(MIN) = + 0.1V - 0.1V = 4.3 V 1 - 1.5 x 450ns 1.7s
PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSP and CSN directly across the current-sense resistor (RSENSE). * When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low side MOSFET or between the inductor and the output filter capacitor. * Route high-speed switching nodes (BOOT, PHASE, UGATE, and LGATE) away from sensitive analog areas (REF, FB, and ILIM).
Special Layout Considerations for LDO Section
The 20F output cap (or caps) at VTT should be placed as close to the VTT and PGND2 pins (pins 12 and 11) as possible to minimize the series resistance/inductance in the trace. The PGND2 side of the cap should be shorted with the lowest impedance path to the ground slug underneath the IC, which should also be star-connected to the GND (pin 24) of the IC. A narrower trace can be used to tie the output voltage on the VTT side of the cap back to the VTTS pin (pin 9). However, keep this trace well away from noisy signals such as the PGND or PGND2 to prevent noise from being injected into the error amplifier's input. For best performance, the VTTI bypass cap should also be placed as close to the VTTI pin (pin 13) as possible. A short low impedance connection should also be made to tie the other side of the cap to the PGND2 pin. The REFIN pin (pin 14) should be separately routed with a clean trace and adequately bypass to AGND. A suggested layout of the board can be found in Evaluation Board Kit of ISL88550A.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the topside of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 24
FN6168.0 October 12, 2005
ISL88550A Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 0 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D D/2 0.15 C A
L28.5x5B
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WHHD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd 0.20 0.50 3.15 3.15 0.20 MIN 0.70 NOMINAL 0.75 0.02 0.55 0.20 REF 0.25 5.00 BSC 4.75 BSC 3.25 5.00 BSC 4.75 BSC 3.25 0.50 BSC 0.55 28 7 7 0.60 12 0.60 3.35 3.35 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5,8 9 7,8 9 7,8 8 2 3 3 9 9 Rev. 0 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
9
Ne P
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
L1 e CC
10
L L1 e
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
25
FN6168.0 October 12, 2005

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